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Verilog : Timing Controls
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Timing Controls

Delay Control Not synthesizable

This specifies the delay time units before a statement is executed during simulation. A delay time of zero can also be specified to force the statement to the end of the list of statements to be evaluated at the current simulation time.

      #delay statement;


Verilog Event Control Example

Event Control, @
This causes a statement or begin-end block to be executed only after specified events occur. An event is a change in a variable. and the change may be: a positive edge, a negative edge, or either (a level change), and is specified by the keyword posedge, negedge, or no keyword respectively. Several events can be combined with the or keyword. Event specification begins with the character @and are usually used in always statements.
For synthesis one cannot combine level and edge changes in the same list.

For flip-flop and register synthesis the standard list contains only a clock and an optional reset.
For synthesis to give combinational logic, the list must specify only level changes and must contain all the variables appearing in the right-hand-side of statements in the block.


    @ (posedge variable or negedge variable) statement;
    @ (variable or variable . . .) statement;


Verilog Timing Delay Control Example

Wait Statement Not synthesizable
The wait statement makes the simulator wait to execute the statement(s) following the wait until the specified condition evaluates to true. Not supported for synthesis.


wait (condition_expression) statement;

Verilog Wait Statement Example

Intra-Assignment Delay Not synthesizable
This delay #D is placed after the equal sign. The left-hand assignment is delayed by the specified time units, but the right-hand side of the assignment is evaluated before the delay instead of after the delay. This is important when a variable may be changed in a concurrent procedure.


variable = #Dt expression;

Verilog Wait Statement Example

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