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Verilog : Test Benches
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Test Benches
A test bench supplies the signals and dumps the outputs to simulate a Verilog design (module(s)). It invokes the design under test, generates the simulation input vectors, and implements the system tasks to view/format the results of the simulation. It is never synthesized so it can use all Verilog commands.
 To view the waveforms when using Cadence Verilog XL Simulator, use the Cadence-specific Simulation History Manager (SHM) tasks of $shm_open to open the file to store the waveforms, and $shm_probe to specify the variables to be included in the waveforms list. You can then use the Cadence cwaves waveform viewer by typing cwaves & at the UNIX prompt.

Syntax
  $shm_open(filename);
  $shm_probe(var1, var2, ...)
Note also
 var=$random
  wait(condition) statement

 

Verilog test benches example

Synchronous Test Bench
In synchronous designs, one changes the data during certain clock cycles. In the previous test bench one had to keep counting delays to be sure the data came in the right cycle. With a synchronous test bench the input data is stored in a vector or array and one part injected in each clock cycle. The Verilog array is not defined in these notes.

Synchronous test benches are essential for cycle based simulators which do not use any delays smaller than a clock
cycle.

Things to note:
data[8:1]=8'b1010_1101;
The underscore visually separates the
bits. It acts like a comment.
if (I==9) $finish
When the data is used up, finish
x<=data[I]; I<=I+1;
When synthesizing to flip-flops as in an
In an @(posedge... procedure,
 always use nonblocking. Without that
you will be racing with the flip-flops in
the other modules.

 

Verilog synchronous test benches example

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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