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Verilog : Tasks
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Tasks Not Synthesizable
A task is similar to a function, but unlike a function it has both input and output ports. Therefore tasks do not return values. Tasks are similar to procedures in most programming languages. The syntax and statements allowed in tasks are those specified for functions (Sections 11).

Syntax 
  task task_name;
    input [msb:lsb] input_port_list;
    output [msb:lsb] output_port_list;
    reg [msb:lsb] reg_variable_list;
    parameter [msb:lsb] parameter_list;
    integer [msb:lsb] integer_list;
             ... statements ...
  endtask

 

Verilog Tasks Example

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