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Verilog : System Tasks and Functions
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System Tasks and Functions
These are tasks and functions that are used to generate input and output during simulation. Their names begin with a dollar sign ($). The Synopsys Verilog HDL Compiler/Design Compiler and many other synthesis tools parse and ignore system functions, and hence can be included even in synthesizable models. Refer to Cadence Verilog-XL Reference Manual for a complete listing of system functions. A few are briefly described here.

System tasks that extract data, like $monitor need to be in an initial or always block.

$display, $strobe, $monitor
These commands have the same syntax, and display their values as text on the screen during simulation. They are much less convenient than waveform display tools like cwaves® or Signalscan®. $display and $strobe display once every time they are executed, whereas $monitor displays every time one of its parameters changes. The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current simulation time unit. The format string is like that in C/C++, and may contain format characters. Format characters include %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time). Append b, h, o to the task name to change default format to binary, octal or hexadecimal.

Syntax
      $display (“format_string”,
                    par_1, par_2, ... );

 

Verilog $display, $strobe, $monitor Example



$time, $stime, $realtime
These return the current simulation time as a 64-bit integer, a 32-bit integer, and a real number, respectively.

$reset, $stop, $finish
$reset resets the simulation back to time 0; $stop halts the simulator and puts it in the interactive mode where the user can enter commands; $finish exits the simulator back to the operating system.

$deposit
$deposit sets a net to a particular value.

Syntax

      $deposit (net_name, value);

 

Verilog $deposit Example


  
$scope, $showscope
$scope(hierarchy_name) sets the current hierarchical scope to hierarchy_name. $showscopes(n) lists all modules, tasks and block names in (and below, if n is set to 1) the current scope.

$list
$list (hierarchical_name) lists line-numbered source code of the named module, task, function or named-block.

$random
$random generates a random integer every time it is called. If the sequence is to be repeatable, the first time one invokes random give it a numerical argument (a seed). Otherwise the seed is derived from the computer clock.

Syntax

  xzz = $random[(integer)];

 

Verilog $random Example


 
$dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall
These can dump variable changes to a simulation viewer like cwaves®. The dump files are capable of dumping all the variables in a simulation. This is convenient for debugging, but can be very slow.

Syntax

$dumpfile(“filename.dmp”)
$dumpvar dumps all variables in the
design.
$dumpvar(1, top) dumps all the varia-
bles in module top and below, but not
modules instantiated in top.
$dumpvar(2, top) dumps all the varia-
bles in module top and 1 level below.
$dumpvar(n, top) dumps all the varia-
bles in module top and n-1 levels below.
$dumpvar(0, top) dumps all the varia-
bles in module top and all level below.
$dumpon initiates the dump.
$dumpoff stop dumping.

Verilog $deposit Example


 
$shm_probe, $shm_open
These are special commands for the Simulation History Manager for Cadence cwaves® only. They will save variable changes for later display.

Syntax

$shm_open (“cwave_dump.dm”)
$shm_probe (var1,var2, var3);
/* Dump all changes in the above 3 varia-
bles. */
$shm_probe(a, b, inst1.var1, inst1.var2);
/* Use the qualifier inst1. to look inside
the hierarchy. Here inside module
instance “inst1” the variables var1 and
var2 will be dumped.*/

 

Verilog $dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall Example

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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