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Verilog : Procedures
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Procedures: Always and Initial Blocks
Always Block
    The always block is the primary construct in RTL modeling. Like the continuous assignment, it is a concurrent statement that is continuously executed during simulation. This also means that all always blocks in a module execute simultaneously. This is very unlike conventional programming languages, in which all statements execute sequentially. The always block can be used to imply latches, flip-flops or combinational logic. If the statements in the always block are enclosed within begin ... end, the statements are executed sequentially. If enclosed within the fork ... join, they are executed concurrently (simulation only).
    The always block is triggered to execute by the level, positive edge or negative edge of one or more signals (separate signals by the keyword or). A double-edge trigger is implied if you include a signal in the event list of the always statement. The single edge-triggers are specified by posedge and negedge keywords.
    Procedures can be named. In simulation one can disable named blocks. For synthesis it is mainly used as a comment.

Syntax 1

      always @(event_1 or event_2 or ...)

       begin

       end


    Syntax 2
      always @(event_1 or event_2 or ...)
         begin: name_for_block
           ... statements ...
         end

Verilog Procedure Always Block Example


Initial Block
The initial block is like the always block except that it is executed only once at the beginning of the simulation. It is typically used to initialize variables and specify signal waveforms during simulation. Initial blocks are not supported for synthesis.
  

Syntax

      initial

         begin

           ... statements ...

        end

Verilog Procedure Initial Block Example

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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