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Verilog : Operators
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Operators


Arithmetic Operators
These perform arithmetic operations. The + and - can be used as either unary (-z) or binary (x-y) operators.

Operators

+     (addition)

-     (subtraction)

*     (multiplication)

/     (division)

%     (modulus)

Verilog Arithmatic Operator Example


Relational Operators
Relational operators compare two operands and return a single bit 1or 0. These operators synthesize into comparators.

Wire and reg variables are positive Thus (-3’b001) = = 3’b111 and (-3d001)>3d110. However for integers -1< 6.

Operators

<     (less than)

<=    (less than or equal to)

>     (greater than)

>=    (greater than or equal to)

==    (equal to)

!=    (not equal to)

Verilog Relational Operator Example


 Bit-wise Operators
Bit-wise operators do a bit-by-bit comparison between two operands. However see“Reduction Operators” on p. 7.

Operators

~        (bitwise NOT)

&        (bitwise AND)

|        (bitwise OR)

^        (bitwise XOR)

~^ or ^~(bitwise XNOR)
Verilog Bit Wise Operator Example


Logical Operators
Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for single bit operands. They can work on expressions, integers or groups of bits, and treat all values that are nonzero as “1”. Logical operators are typically used in conditional (if ... else) statements since they work with expressions.

Operators

! (logical NOT)

&& (logical AND)

|| (logical OR)

Verilog Logical Operator Example


Reduction Operators
Reduction operators operate on all the bits of an operand vector and return a single-bit value. These are the unary (one argument) form of the bit-wise operators above.

Operators

&       (reduction AND)

|       (reduction OR)

~& (reduction NAND)

~|      (reduction NOR)

^       (reduction XOR)

~^ or ^~(reduction XNOR)

Verilog Reductioc Operator Example


 Shift Operators
Shift operators shift the first operand by the number of bits specified by the second operand. Vacated positions are filled with zeros for both left and right shifts (There is no sign extension).

Operators

<< (shift left)

>> (shift right)

Verilog Shift Operator Example


Concatenation Operator
The concatenation operator combines two or more operands to form a larger vector.

Operators

{ } (concatenation)

Verilog Concatenation Operator Example


Replication Operator

The replication operator makes multiple copies of an item.

Operators

{n{item}} (n fold replication of an item)

For synthesis, Synopsis did not like a zero replication. For example:-
           parameter n=5, m=5;
           assign x= {(n-m){a}}

 

Verilog Replication Operator Example


Conditional Operator: “?”
Conditional operator is like those in C/C++. They evaluate one of the two expressions based on a condition. It will synthesize to a multiplexer (MUX).

Operators

(cond) ? (result if cond true):

              (result if cond false)

Verilog Conditional Operator Example


Operator Precedence
Table below shows the precedence of operators from highest to lowest. Operators on the same level evaluate from left to
right. It is strongly recommended to use parentheses to define order of precedence and improve the readability of
your code.

Operator Precedance Table

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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Posted By : SANTHOSH G - Jan. 6, 2010, 4:01 p.m.

thanks for providing this topic in simple manner. very simple n easy to understand. once again thanks sir.

 
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