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Verilog : Modules
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Modules


Module Declaration
A module is the principal design entity in Verilog. The first line of a module declaration specifies the name and port list (arguments). The next few lines specifies the i/o type (input, output or inout, see Sect. 4.4. ) and width of each port. The default port width is 1 bit.
Then the port variables must be declared wire, wand,. . ., reg (See Sect. 4. ). The default is wire. Typically inputs are wire since their data is latched outside the module. Outputs are type reg if their signals were stored inside an always or initial block (See Sect. 10. ).

Syntax

module module_name (port_list);
  input [msb:lsb] input_port_list;
  output [msb:lsb] output_port_list;
  inout [msb:lsb] inout_port_list;
         ... statements ...
endmodule

Verilog Module Description Examples


  
Continuous Assignment
The continuous assignment is used to assign a value onto a wire in a module. It is the normal assignment outside of always or initial blocks (See Sect. 10. ). Continuous assignment is done with an explicit assign statement or by assigning a value to a wire during its declaration. Note that continuous assignment statements are concurrent and are continuously executed during simulation. The order of assign statements does not matter. Any change in any of the right-hand-side inputs will immediately change a left-hand-side output.

Syntax

wire wire_variable = value;
assign wire_variable = expression;

 

Verilog Module Continuous Assignment Examples

Module Instantiations
Module declarations are templates from which one creates actual objects (instantiations). Modules are instantiated inside other modules, and each instantiation creates a unique object from the template. The exception is the top-level module which is its own instantiation.
 The instantiated module’s ports must be matched to those defined in the template. This is specified:
(i) by name, using a dot(.) “ .template_port_name (name_of_wire_connected_to_port )”. or

(ii) by position, placing the ports in exactly the same positions in the port lists of both the template and the instance.

Syntax for Instantiation

module_name
 instance_name_1 (port_connection_list),
 instance_name_2 (port_connection_list),

.......
instance_name_n (port_connection_list);

 

Verilog Module Instantiations Example

                        Modules may not be instantiated inside procedural blocks.

Parameterized Modules
You can build modules that are parameterized and specify the value of the parameter at each instantiation of the module. See “Parameter” on page 5 for the use of parameters inside a module. Primitive gates have parameters which have been predefined as delays. See “Basic Gates” on page 3.

Syntax

module_name #(parameter_values)

instance_name(port_connection_list);

 

Verilog Parameterized Modules Example


Synthesis does not support the defparam keyword which is an alternate way of changing parameters.

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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Next >> Behavioral Modeling

 
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