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Verilog : Functions
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Functions
Functions are declared within a module, and can be called from continuous assignments, always blocks or other functions. In a continuous assignment, they are evaluated when any of its declared inputs change. In a procedure, they are evaluated when invoked.
Functions describe combinational logic, and by do not generate latches. Thus an if without an else will simulate as though it had a latch but synthesize without one. This is a particularly bad case of synthesis not following the simulation. It is a good idea to code functions so they would not generate latches if the code were used in a procedure.
Functions are a good way to reuse procedural code, since modules cannot be invoked from a procedure.

Function Declaration
A function declaration specifies the name of the function, the width of the function return value, the function input arguments, the variables (reg) used within the function, and the function local parameters and integers.

Syntax, Function Declaration
  function [msb:lsb] function_name;
    input [msb:lsb] input_arguments;
    reg [msb:lsb] reg_variable_list;
    parameter [msb:lsb] parameter_list;
    integer [msb:lsb] integer_list;
             ... statements ...
  endfunction

 

Verilog Function Declaration Example


  Function Return Value
When you declare a function, a variable is also implicitly declared with the same name as the function name, and with the width specified for the function name (The default width is 1-bit). This variable is “my_func” . At least one statement in the function must assign the function return value to this variable.
Function Call
A function call is an operand in an expression. A function call must specify in its terminal list all the input parameters.
Function Rules
The following are some of the general rules for functions:
   - Functions must contain at least one input argument.
   - Functions cannot contain an inout or output declaration.
   - Functions cannot contain time controlled statements (#, @, wait).
   - Functions cannot enable tasks.
   - Functions must contain a statement that assigns the return value to the implicit function name register.

Function Example
A Function has only one output. If more than one return value is required, the outputs should be concatenated into one vector before assigning it to the function name. The calling module program can then extract (unbundle) the individual outputs from the concatenated form. Example 11.2 shows how this is done, and also illustrates the general use and syntax of functions in Verilog modeling.

Syntax

function_name = expression

Verilog Function Example

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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