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Verilog : Finite State Machines
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Finite State Machines. For synthesis
When modeling finite state machines, it is recommended to separate the sequential current-state logic from the com- binational next-state and output logic.

State Diagram 
for lack of space the outputs are not
shown on the state diagram, but are:
  in state0: Zot = 000,
  in state1: Zot = 101,
  in state2: Zot = 111,
  in state3: Zot = 001.
Verilog Finite State Machine Block Diagram

Using Macros for state definition

As an alternative for-

parameter state0=0, state1=1,
             state2=2, state3=3;
one can use macros. For example after the
definition below 2'd0 will be textually
substituted whenever `state0 is used.
 `define state0 2'd0
 `define state1 2'd1
 `define state2 2'd
 `define state3 2'd3;

When using macro definitions

one must put a back quote in front. For example:
case (state)
       `state0: Zot = 3’b000;
       `state1: Zot = 3’b101;
       `state2: Zot = 3’b111;
       `state3: Zot = 3’b001;

Verilog Finite State Machine Example

Counters are a simple type of finite-state machine where separation of the flip-flop generation code and the next-state generation code is not worth the effort. In such code, use the nonblocking “<=” assignment operator.

  Binary Counter
    Using toggle flip-flops

Verilog Counter Block Diagram

Verilog Counter Example

Shift Registers
Shift registers are also best done completely in the flip-flop generation code. Use the nonblocking “<=” assignment operator so the operators “<< N” shifts left N bits. The operator “>>N” shifts right N bits.

Shift Register

Verilog Shift Register Block Diagram

Linear-Feedback Shift Register

Verilog Linear-Feedback Shift Register Block Diagram


Verilog Shift Register Example
Verilog Linear-Feedback Shift Register Example

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

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