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Verilog : Component Inference
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Component Inference
A latch is inferred (put into the synthesized circuit) if a variable is not assigned to in the else branch of an if ... else if ... else statement. A latch is also inferred in a case statement if a variable is assigned to in only some of the possible case choice branches. Assigning a variable in the default branch avoids the latch. In general, a latch is inferred in if ... else if ... else and case statements if a variable, or one of its bits, is only assigned to in only some of the possible branches.

To improve code readability, use the if statement to synthesize a latch because it is difficult to explicitly specify the
latch enable signal when using the case statement.

  same as
  if ... else if ... else and case statements


Verilog Latches Example

Edge-Triggered Registers, Flip-flops, Counters
A register (flip-flop) is inferred by using posedge or negedge clause for the clock in the event list of an always block.
To add an asynchronous reset, include a second posedge/negedge for the reset and use the if (reset) ... else statement.
Note that when you use the negedge for the reset (active low reset), the if condition is ( !reset).

  always @(posedge clk or
              posedge reset_1 or
              negedge reset_2)
      if (reset_1) begin
                    ... reset assignments
      else if (!reset_2) begin
                    ... reset assignments
      else         begin
                    ...register assignments


  Verilog Flip Flops Counters Example
Verilog Flip Flops Counters Example

A multiplexer is inferred by assigning a variable to different variables/values in each branch of an if or case statement. You can avoid specifying each and every possible branch by using the else and default branches. Note that a latch will be inferred if a variable is not assigned to for all the possible branch conditions.
To improve readability of your code, use the case statement to model large multiplexers.

  same as
  if ... else if ... else and case statements


Verilog Multiplexers Example

The +/- operators infer an adder/subtracter whose width depend on the width of the larger operand.


Same as operator


Verilog Adder/Substractor Example

Tri-State Buffers
A tristate buffer is inferred if a variable is conditionally assigned a value of z using an if, case or conditional operator.

  same as
  if ... else if ... else and case statements

Verilog Tri state Buffer Example

Other Component Inferences
Most logic gates are inferred by the use of their corresponding operators. Alternatively a gate or component may be explicitly instantiated by using the primitive gates (and, or, nor, inv ...) provided in the Verilog language.

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

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