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Verilog : Compiler Directives
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Compiler Directives
Compiler directives are special commands, beginning with ‘, that affect the operation of the Verilog simulator. The Synopsys Verilog HDL Compiler/Design Compiler and many other synthesis tools parse and ignore compiler directives, and hence can be included even in synthesizable models. Refer to Cadence Verilog-XL Reference Manual for a complete listing of these directives. A few are briefly described here.


Time Scale
`timescale specifies the time unit and time precision. A time unit of 10 ns means a time expressed as say #2.3 will have a delay of 23.0 ns. Time precision specifies how delay values are to be rounded off during simulation. Valid time units include s, ms, μs, ns, ps, fs. Only 1, 10 or 100 are valid integers for specifying time units or precision. It also determines the displayed time units in display commands like $display

   Syntax
     `timescale time_unit / time_precision;

 

Verilog Compiler directives Example

 
Macro Definitions
A macro is an identifier that represents a string of text. Macros are defined with the directive `define, and are invoked with the quoted macro name as shown in the example.

Syntax

     `define macro_name text_string;
     . . . `macro_name . . .

 

Verilog Macro Definitios Example

 
Include Directive
Include is used to include the contents of a text file at the point in the current file where the include directive is. The include directive is similar to the C/C++ include directive.

   Syntax
     `include file_name;

 

Verilog Include directives Example

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