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Declare reigsters and flip flops
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Declare reigsters and flip flops :

reg [0:7] A, B;

reg       C;

 

// The two "initial"s and "always" will run concurrently

initial begin: stop_at

   // Will stop the execution after 20 simulation units.

   #20; $stop;   

end

 

// These statements done at simulation time 0 (since no #k)

initial begin: Init

    // Initialize register A.  Other registers have values of "x"

    A = 0;  

  

    // Display a header

    $display("Time   A         B    C"); 

            

    // Prints the values anytime a value of A, B or C changes

    $monitor("  %0d %b %b %b", $time, A, B, C);

end

 

//main_process will loop until simulation is over

always begin: main_process

 

    // #1 means do after one unit of simulation time

    #1 A = A + 1;

    #1 B[0:3] = ~A[4:7]; // ~ is bitwise "not" operator

    #1 C = &A[6:7];      // bitwise "and" reduction of last 2 bits

of A

   

end

 

endmodule

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

 
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