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Regular expression in System Verilog
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System verilog regular expressions : 

System verilog does not have very good regular expression support inbuilt. You can only use the string inbuilt functions to get the expected results you want.

Few useful string functions for parsing strings are :

integer result = string.compare(str); string substring = string.substr(start,end);

You can use this functions to perform get the required string.

Stripping/removing the new line character from the string :

You can simply remove the new line character using the following code :

line = line.substr(0,line.len()-2);

Stripping the front spaces from the string :

    while (line.substr(0,0) == " ") begin

        line = line.substr(1, line.len()-1); $display("LINE IS (%s)", line);

    end


Stripping the trail spaces from the string :


    while (line.substr(line.len()-1, line.len()-1) == " ") begin

        line = line.substr(0, line.len()-2); $display("LINE IS (%s)", line);

    end

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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