Home System Verilog Constructs Randomization
Main Menu
Home
System Verilog
    - Constructs
        -- Introduction
        -- Data Types
        -- Type Casting
        -- SV Arrays
        -- Assoc Arrays
        -- Dynamic Array
        -- Queues
        -- Operators
        -- Procedural statements
        -- Classes
        -- OOP Concepts
        -- Inter process communication
        -- Randomization
        -- Interface
        -- Clocking block
        -- Conststraits
        -- Coverage
        -- DPI
        -- Regular expression
        -- Files
    - SV Classes
    - Functional Coverage SV
    - Examples
    - Tools
    - Links
    - Books
    - Interview Questions SV
Verilog
Methodologies
Open Vera
Digital Concepts
Verification Basics
Protocols
Scripting
Articles
Videos
Interview Questions
Computer Architechture
C and C++
Blog/Article
AsicGuru Blog
Tags Cloud
Ads
Usefull Sites
Know Your IP/Location
Local Information India
Buy Car/Inverter Batteries
Real Estate India
Sports Accessories India
Randomization In System Verilog
Share This Articale:

Randomization :

System verilog allows object oriented ways of random stimulus generation.

Why Do we need randomization :

  -- Driving Random stimulus to DUT by changing the characterstics of data

  -- Random setting of parameters (select ports, parameters, addresses randomly)

  -- Hard to test corner cases can be reached

Random test behaviour depends upon the SEED. If you run the same test case with same SEED you will get the same behaviour but if you run the same testcase with different SEED you will get different behavior. Its eqvivalent to running different testcases.

Directed testing detects expected bugs where as the random testing exptects the unexpected bugs (corner cases). It reduces the efforts.

Randomization Example :

program automatic test;

  class Transaction;

    rand bit [31:0] src, dst, data[]; // Dynamic array
    randc bit [2:0] kind; // Cycle through all kinds
    constraint c_len
    { 
       data.size inside {[1:1000]}; 
    } // Limit array size
  endclass

  Transaction tr;

  initial begin
    tr = new();
    assert(tr.randomize());
    send(tr);
  end

endprogram

Random Variables :

Random variables can be defined by appending rand or randc in front of variables.

rand – returns values over the entire range
randc – random cyclic value up to 16 bits

Object variables are randomized by randomize()
-- The method is automatically available to classes with random variables.
-- Returns a 1 upon success, 0 on failure

** Always check randomize ()


Optional: pre_randomize() & post_randomize() void
functions which will be called automatically
-- pre_randomize() – set up random weights
-- post_randomize() – cleanup calculations

 

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


Prev << Inter process communication

Next >> Interface

 
Login/Register
Register
Sign In
Login with :-
gmail-yahoo-twitter-facebook
| | |  
  •  
  • Bookmark
    ADS