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System Verilog Statements and control flow
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Procedural statements and Control flow:

A procedural statement can be added in system verilog using :

  1. initial // enable this statement at the beginning of simulation and execute it only once
  2. final // do this statement once at the end of simulation
  3. always, always_comb, always_latch, always_ff // loop forever
  4. task // do these statements whenever the task is called
  5. function // do these statements whenever the function is called and return a value

SystemVerilog has the following types of control flow within a process:
— Selection, loops, and jumps
— Task and function calls
— Sequential and parallel blocks
— Timing control

Blocking and Non Blocking Statement :

Following type of statement is allowed in both verilog and system verilog.

#1 r = a;
r = #1 a;
r <= #1 a;
r <= a;
@c r = a;

r = @c a;
r <= @c a;

SystemVerilog also allows a time unit to be specified in the assignment statement, as follows:

#1ns r = a;

r = #1ns a;

r <= #1ns a;

* Its illegal to make non blocking assignments to automatic variables

* If size of the left hand size is smaller than right hand size information will be lost

Selection Statements :

1. IF ELSE statement :

if ((a==0) || (a==1)) 
    $display("0 or 1");
else if (a == 2) 
else if (a == 4) $display("4");

2. Case Statement


bit [2:0] a;

unique case(a) // values 3,5,6,7 cause a warning
   0,1: $display("0 or 1");
   2: $display("2");
   4: $display("4");

priority casez(a) 
    // values 4,5,6,7 cause a warning
    3’b00?: $display("0 or 1");
    3’b0??: $display("2 or 3");

SystemVerilog adds the keywords unique and priority, which can be used before an if. If either keyword
is used, it shall be a warning for no condition to match unless there is an explicit else.

For example:

unique if ((a==0) || (a==1)) 
    $display("0 or 1");
else if (a == 2) 
else if (a == 4) 
    // values 3,5,6,7 cause a warning

// Priority 

priority if (a[2:1]==0) 
    $display("0 or 1");
else if (a[2] == 0) 
    $display("2 or 3");
else $display("4 to 7"); //covers all other possible values, so no warning

Loops :

1. do...while loop

while(condition) // as C

The condition can be any expression that can be treated as a boolean. It is evaluated after the statement


2. For Loop

SystemVerilog adds the ability to declare the for loop control variable within the for loop. This creates a local variable within the loop. Other parallel loops cannot inadvertently affect the loop control variable. For example:

    for (int i = 0; i <= 255; i++)
        $display("I = %d \n", i);

The local variable declared within a for loop is equivalent to declaring an automatic variable in an unnamed block.

3. Foreach loop

The foreach construct specifies iteration over the elements of an array. Its argument is an identifier that
designates any type of array (fixed-size, dynamic, or associative) followed by a list of loop variables
enclosed in square brackets. Each loop variable corresponds to one of the dimensions of the array. The
foreach construct is similar to a repeat loop that uses the array bounds to specify the repeat count instead of an expression.

string words [2] = '{ "hello", "world" };
int prod [1:8] [1:3];
foreach( words [ j ] )
    $display( j , words[j] ); 
    // print each index and value

foreach( prod[ k, m ] )
   prod[k][m] = k * m; // initialize

Jump Statement :

SystemVerilog adds the C jump statements break, continue, and return.
break                    // out of loop as C
continue               // skip to end of loop as C
return expression   // exit from a function
return                    // exit from a task or void function

The continue and break statements can only be used in a loop. The continue statement jumps to the end of the loop and executes the loop control if present. The break statement jumps out of the loop. The continue and break statements cannot be used inside a fork...join block to control a loop outside the
fork...join block. The return statement can only be used in a task or function. In a function returning a value, the return must have an expression of the correct type.

Final Block :

The final block is like an initial block, defining a procedural block of statements, except that it occurs
at the end of simulation time and executes without delays. A final block is typically used to display statistical  information about the simulation.

The only statements allowed inside a final block are those permitted inside a function declaration. This
guarantees that they execute within a single simulation cycle. Unlike an initial block, the final block
does not execute as a separate process; instead, it executes in zero time, the same as a function call.

A final block executes when simulation ends due to an explicit or implicit call to $finish.
    $display("Number of cycles executed %d",$time/period);
    $display("Final PC = %h",PC);

Disable Statement :

SystemVerilog has break and continue to break out of or continue the execution of loops. The Verilog
disable can also be used to break out of or continue a loop, but is more awkward than using break or
continue. The disable is also allowed to disable a named block, which does not contain the disable
statement. If the block is currently executing, this causes control to jump to the statement immediately after the block. If the block is a loop body, it acts like a continue. If the block is not currently executing, the disable has no effect.

SystemVerilog has return from a task, but disable is also supported. If disable is applied to a named
task, all current executions of the task are disabled.
module ...
always always1: begin ... t1: task1( ); ... end
always begin
disable u1.always1.t1; // exit task1, which was called from always1

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