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Introduction To System Verilog
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What is System Verilog :

  1. SystemVerilog is a hardware description and Verification language(HDVL)
  2. SystemVerilog is an extensive set of enhancements to IEEE 1364 Verilog-2001 standards
  3. It has features inherited from Verilog HDL,VHDL,C,C++
  4. Adds extended features to verilog
  5. System verilog is the superset of verilog
  6. It supports all features of verilog plus add on features
  7. It’s a super verilog
  8. + More additional features

Introduction to system verilog

SystemVerilog is a Hardware Description and Verification Language based on Verilog. Although it has some features to assist with design, the thrust of the language is in verification of electronic designs. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. SystemVerilog has just become IEEE standard P1800-2005


SystemVerilog is an extension of Verilog-2001; all features of that language are available in SystemVerilog. The remainder of this article discusses the features of SystemVerilog not present in Verilog-2001


This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

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