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System Verilog Data Types Overview :

SystemVerilog DataTypes Overview

1. Integer or Basic Data Types - System verilog has a hybrid of both verilog and C data types

  1. shortint - 2-state SystemVerilog data type, 16-bit signed integer
  2. int - 2-state SystemVerilog data type, 32-bit signed integer
  3. longint - 2-state SystemVerilog data type, 64-bit signed integer
  4. byte - 2-state SystemVerilog data type, 8-bit signed integer or ASCII character
  5. bit - 2-state SystemVerilog data type, user-defined vector size
  6. logic - 4-state SystemVerilog data type, user-defined vector size
  7. reg - 4-state Verilog data type, user-defined vector size
  8. integer - 4-state Verilog data type, 32-bit signed integer
  9. time - 4-state Verilog data type, 64-bit unsigned integer

Integral Types -

The term integral is used to refer to the data types that can represent a single basic integer data type, packed array, packed struct, packed union, enum, or time

2 Stage and 4 State Data Types -

Types that can have unknown and high-impedance values are called 4-state types. These are logic, reg, integer, and time. The other types do not have unknown values and are called 2-state types, for example, bit and int.

The difference between int and integer is that int is a 2-state type and integer is a 4-state type. The 4- state values have additional bits that encode the X and Z states. The 2-state data types can simulate faster, take less memory, and are preferred in some design styles.

Signed and unsigned Data Types - 

Integer types use integer arithmetic and can be signed or unsigned. This affects the meaning of certain oper-
ators such as ‘<’, etc.

   int unsigned ui;

   int signed si;

The data types byte, shortint, int, integer, and longint default to signed. The data types bit, reg,
and logic default to unsigned, as do arrays of these types.

Real and short real data types -

The real7 data type is from Verilog and is the same as a C double. The shortreal data type is a System- Verilog data type and is the same as a C float.
Candle data types - 
The chandle data type represents storage for pointers passed using the DPI. The size of a value of this data type is platform dependent, but shall be at least large enough to hold a pointer on the machine in which the tool is running.
The syntax to declare a handle is as follows:
     chandle variable_name ;

where variable_name is a valid identifier. Chandles shall always be initialized to the value null, which has a value of 0 on the C side. Chandles are very restricted in their usage, with the only legal uses being as follows:

       —    Only the following operators are valid on chandle variables:
        —     Equality (==), inequality (!=) with another chandle or with null
        —     Case equality (===), case inequality (!==) with another chandle or with null (same seman-
              tics as == and !=)
   —    Chandles can be tested for a boolean value that shall be 0 if the chandle is null and 1 otherwise.
   —    Only the following assignments can be made to a chandle:
        —     Assignment from another chandle
        —     Assignment to null

String Data Types -

SystemVerilog includes a string data type, which is a variable size, dynamically
allocated array of bytes. SystemVerilog also includes a number of special methods
to work with strings.
Variables of type string can be indexed from 0 to N-1 (the last element of the
array), and they can take on the special value “”, which is the empty string. Reading
an element of a string yields a byte.
string myName = "John Smith";
If an initial value is not specified in the declaration, the variable is initialized to “”,
the empty string.
A string literal can be assigned to a string or an integral type. If their size differs the
literal is right justified and either truncated on the left or zero filled on the left, as
necessary. For example:

byte c = "A"; // assign to c "A"

bit [10:0] a = "\x41"; // assigns to a ‘b000_0100_0001

bit [1:4][7:0] h = "hello" ; // assigns to h "ello"

Event Data type -

The system verilog events are enhanced in a number of ways and they are backward compatible with verilog static events.
In system verilog you can wait for an event either using the @ sign or wait operator as well and the events are triggered using the -> and ->> operators

an event :
You can trigger an event using -> sign
It will unblock all processes waiting for that event. when triggered they will behave like ONE_SHOT i.e trigger state is not obserable only its effect.

Non Blocking event trigger :
Non blocking events are triggered using the operator ->>
The effect of ->> is that the statement executes without blocking and it creates a not blocking assign update event in the time in which they delay control expires or the event control occurs.

Waiting for an event :
you can wait for an event using @ operator
The @ operator blocks the calling process untill the given event is triggered
The waiting process must execute the @ before the -> executes otherwise the process will keep waiting for that.

User Defined Data types -

New data types can be defined using the C type typedef's
typedef int myint;
myint a, bl

Enumerations -

Enumerated data types allows meaning full names to be assigned to numeric quantities. Variables declared as enumerated can not be assigned to
variable of different enumerated type without type casting. Following is example of enumerated data type decleration.

enum {red, yellow, green} light1, light2; // anonymous int type

enum {bronze=3, silver, gold} medal; // silver and gold will be assigned 4 and 5
enum {a=0, b=7, c, d=8} alphabet; // syntax error both c and d will be assigned 8 

Its better to avoid X, Z assignment in the enumeration decleration. It sometimes causes the syntax error. Look in the LRM for more details buts its better to avoid.

Defining new data types as enumerated types

A type name can be given so that the same type can be used in many places.
typedef enum {NO, YES} boolean;
boolean myvar; // named type

A range of enumeration elements can be specified automatically, via the syntax :

For example:
typedef enum { add=10, sub[5], jmp[6:8] } E1;

This example defines the enumerated type E1, which assigns the number 10 to the enumerated named constant
add. It also creates the enumerated named constants sub0, sub1, sub2, sub3, and sub4 and assigns
them the values 11...15, respectively. Finally, the example creates the enumerated named constants jmp6,
jmp7, and jmp8 and assigns them the values 16 through 18, respectively.


Classes :

A class is a collection of data and subroutines which operate on the data. Data in the class is refered as the properties and subroutines as methods
A class can be declared using the class and endclass keywords

class Packet;
   int address;         // Properties are address, data, and crc
   bit [63:0] data;
   shortint crc;
   Packet next;         // Handle to another Packet
                        // Methods are send and new
   function new();
   function bit send();
endclass : Packet

Structure and Union -

Structure and union follow the same syntax as the C. A struct can be declared as    :

typedef struct {
            bit [7:0] opcode;
            bit [23:0] addr;
} instruction; // named structure type
instruction IR; // define variable

Singular and aggregate data types -

Data types can be categorized as singular and aggregate. As the name suggests a singular data type can be any type expect an unpacked structure, unpacked union or unpacked arrays. A singular data type represent a single value, hanle or symbols.
Aggregate variables represent a set or collection of singular values.

VOID Data Type :

The void data type represents nonexistent data. This type can be specified as the return type of functions to indicate no return value. void = function_call();

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

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