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System Verilog Coverage
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Coverage in Sytem Verilog :

Coverage as applied to hardware verification languages refers to the collection of statistics based on sampling events within the simulation. Coverage is used to determine when the device under test (DUT) has been exposed to a sufficient variety of stimuli that there is a high confidence that the DUT is functioning correctly. Note that this differs
from code coverage which instruments the design code to ensure that all lines of code in the design have been executed. Functional coverage ensures that all desired corner cases in the design space have been explored.

A SystemVerilog coverage group creates a database of "bins" that store a histogram of values of an associated variable. Cross coverage can also be defined, which creates a histogram representing the Cartesian cross-product of multiple variables. A sampling event controls when a sample is taken. The sampling event can be a Verilog event, the entry or exit of a block of code, or a call to the sample method of the coverage group. Care is required to ensure that data is sampled only when meaningful.


class eth_frame;

    // Definitions as above
    covergroup cov;

    coverpoint dest 
       bins bcast[1] = {48'hFFFFFFFFFFFF};
       bins ucast[1] = default;

    coverpoint type 
        bins length[16] = { [0:1535] ];
        bins typed[16] = { [1536:32767] };
        bins other[1] = default;

    psize: coverpoint payload.size 
        bins size[] = { 46, [47:63], 64, [65:511], [512:1023],
        [1024:1499], 1500 };

    sz_x_t: cross type, psize;



In this example, the verification engineer is interested in the distribution of broadcast and unicast frames, the size/type field and the payload size. The ranges in the payload size coverpoint reflect the interesting corner cases, including minimum and maximum size frames.

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

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