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System Verilog Clocking block
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Clocking Block :

- Specify synchronization characteristics of the design

- Offer a clean way to drive and sample signals

- Provides race-free operation if input skew > 0

- Helps in testbench driving the signals at the right time

-  Features

    - Clock specification

    - Input skew,output skew

    - Cycle delay (##)

- Can be declared inside interface,module or program

Example :

Module M1(ck, enin, din, enout, dout);
 input         ck,enin;
 input  [31:0] din    ;
 output        enout  ;
 output [31:0] dout   ;

 clocking sd @(posedge ck);
   input  #2ns ein,din    ;
   output #3ns enout, dout;
 endclocking:sd

 reg [7:0] sab ;
 initial begin
   sab = sd.din[7:0];
 end
endmodule:M1

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