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System Verilog Classes
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System Verilog Classes and OOP :

SystemVerilog provides an object-oriented programming model. Classes are the basis for the object oriented programming. SystemVerilog classes support a single-inheritance model. SystemVerilog classes can be type-parameterized, providing the basic function of C++ templates. However, function templates and template specialization are not supported.

The polymorphism features are similar to those of C++: the programmer may write a virtual function to have a derived class gain control of the function.  Encapsulation and data hiding is accomplished using the local and protected keywords, which must be applied to any item that is to be hidden. By default, all class properties are public.

SystemVerilog class instances are created with the new keyword. A constructor denoted by function new can be defined. SystemVerilog supports garbage collection, so there is no facility to explicitly destroy class instances.

A Simple Class example : 

class simple;
	int len;

	function new (int len);
		this.len = len;
	endfunction : new

	function void print_len ();
		$display("Len is = %d", len);
	endfunction : print_len

endclass 

program main;

	simple objSimple;

	initial 
	begin
		objSimple = new ( 10 ); // Init len variable. And Create object 
		objSimple.print_len(); 	// Call print len function 
	end

endprogram: main

// To compile with vcs give : 
vcs -sverilog simpleClass.sv
// and to run give ./simv

Please on the below links to learn more about classes :

Keywords : classes   oop  

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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