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A simple class example system verilog
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Classes in system verilog :


Classes contains properties and methods. Methods perform operations on the class properties. Class name will be used as type to declare the variable or handle for the class.
Instance for the class is created with the constructor which is new method. When you call the new method memory is allocated to class and its properties. If you dont declare the new method for the class it will be implicitly declared.
An explicit constructor can be created to initialize the properties of the class or for calling up some methods etc. Like if you see in the below example we have created a new method for the class mem_transfer which takes a argument addr_in and initilize the class property addr and data property is initialized to 0.

The properties which are not initialized will take the default values for that datatype. System verilog performs the automatic memory management for you unlike C++ to avoid the memory leaks. System verilog deletes the objects which is no more accessed in the code. Ofcourse you can not play like C++ pointers with system verilog class handles.

By default all the class varialbes (properties) are visible outside. We can access any properties using the dot operator like m1.addr. But if you want to restict the access from outside you can use the local keyword. 

like :

local int addr;

So the statement like objname.addr will cause a error. The feature is called encapsulation. You hide you properties and provide methods to manipulate them

`define ADDR_SIZE 32
`define DATA_SIZE 16

class mem_transfer;

    rand local bit [`ADDR_SIZE-1:0] addr;
    rand bit [`DATA_SIZE-1:0] data;

    rand bit [`DATA_SIZE-1:0] write_enable;
    rand bit chip_enable;

    rand int unsigned size;

    constraint c_size {
        size inside {1, 2, 4, 8};
    }

    constraint c_chip_enable {
        chip_enable == 0;
    }

    // Class Constructor
    function new (bit [`ADDR_SIZE-1:0] addr_in ) ;
        addr = addr_in;
        data = 'b0;
    endfunction : new

   // function print

  function void print ();
      $display ("Addr = %h, Data = %h, WriteEnable = %h", addr, data, write_enable);
  endfunction


endclass : mem_transfer

program test ;
 
mem_transfer m1;
initial
begin
    m1 = new('hFFFF);
    m1.print();
end

endprogram

Compile :
vlib work;
vmap work work
vlog -sv simpleClass.sv
vsim -c test

Output :
# Addr = 0000ffff, Data = 0000, WriteEnable = 0000

Keywords : class   system   verilog  

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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