Parameterized Classes in System Verilog :
System verilog allows prameterized classes. In the system verilog you can parameterize the types also. Its basically like templates in C++. Like in classes can be parameterized for size, width, and more With Verilog parameter notation
Class type can also be a parameter
- Qualified with keyword type
- Define operations which can be used with different types
Each different type parameter creates a different class declaration.
- Separate static members for each different type
Parameterized classes can be extended (inherited).
typedef logic[7:0] vec84;
class stack #(type st = int, depth = 5);
local st data[depth-1:0];
local int pointer;
function int push(input st indat);
...
endfunction
function int pop(output st outdat);
...
endfunction
endclass
// int stack of depth 5 (default)
stack intstack = new();
// 8-bit vector stack, depth 8
stack #(.st(vec8), .depth(8)) bytestack;
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