Class Inheritance In System Verilog :

A class declaration can extend an existing class. Inheritance Subclass inherits all members of parent.
Can over-ride parent's members Parent members are accessed as if they were members of the subclass

class parent;
  logic [3:0] avec;
  logic abit;

  function void print();
    $display("%d %d", avec, abit);
  endfunction

endclass

class child extends parent;
  int avec;    
  byte abyte;

  function void print();
   $display("%0d %b %h", avec, abit, abyte); 
  endfunction

endclass

program test;

child one = new();

initial begin
  one.avec = 0;
  one.abit = 1'b1;
  one.abyte = 8'hff;
  one.print(); // 0 1 ff
end

endprogram

Parent constructor is implicitly called as first line of subclass constructor. Parent constructor must be explicitly called to pass arguments. Must be the first line of subclass constructor Prefix super allows a subclass to access parent members . Otherwise hidden by subclass members

class parent;
  logic p1;

  function new(input logic a1);
    p1 = a1;
  endfunction

endclass

class child extends parent;
  logic c1;

 function new(input logic a1, a2);
    super.new(a1);
    c1 = a2;
 endfunction

 function void print();
    $display("%b %b", p1, c1);
  endfunction
endclass

child one = new(1'b0, 1'b0);

initial begin
  one.b1 = 1'b1;
  one.print();  // 1 0
  ...

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start