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In-Line Constraints in system verilog
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In-Line Constraints in system verilog :

One of the main feature of the systemverilog classes are randomization. You can randomize the system verilog classes with the randomize method using

obj.randomize();

It will randomize all the properties which are declared as rand and randc and can take any valid value for the varialbe. like for variable

rand bit [3:0] a;

A can take any value between 0 - 15.  Constraints can be applied to or used to contol the value generated with randomization. In system verilog constraints can be applied in two ways :

  1. In line constraints
  2. Class constraints

Inline constraints can be attached to randomize using with.

  - Simple relational constraint

  - Change weighting of values with dist

But they are difficult to maintain and a better option is to use subclasses and inheritance.

class randframe;
  local logic [3:0] addr;
  rand local logic [3:0] len;
  logic [7:0] data_arr [];

  function new(input logic [3:0] pa); 
    addr = pa;
  endfunction

  function void post_randomize();
    data_rand();
  endfunction

  ...

endclass

randframe one = new(.pa(5));

initial begin
  assert(one.randomize() with {len>0; len<=7;});
  ...
  assert(one.randomize() with {len dist {[1:7]:=2, [8:15]:=1};});
  ...


This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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