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What are the ways to avoid race condition between testbench and RTL using SystemVerilog
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What are the ways to avoid race condition between testbench and RTL using SystemVerilog :

There are mainly following ways to avoid the race condition between testbench and RTL using system verilog 

1. Program Block

2. Clocking Block

3. Using non blocking assignments.

I will try to explain them one by one but as of now manage with this short answer. If you are in hurry read the program block section of the system verilog LRM.

See this nice explanation by avian efody : http://www.specman-verification.com/?entry=entry081225-125818

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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