Home System Verilog Interview Questions SV Part 2
Main Menu
System Verilog
    - Constructs
    - SV Classes
    - Functional Coverage SV
    - Examples
    - Tools
    - Links
    - Books
    - Interview Questions SV
        -- What is callback
        -- What is factory pattern
        -- Logic Reg wire
        -- Need Clocking Block
        -- Ways to avoid race
        -- Coverage Questions
        -- OOP
        -- Need of virtual interface
        -- abstract class
        -- Part 1
        -- Part 2
Open Vera
Digital Concepts
Verification Basics
Interview Questions
Computer Architechture
C and C++
AsicGuru Blog
Tags Cloud
Usefull Sites
Know Your IP/Location
Local Information India
Buy Car/Inverter Batteries
Real Estate India
Sports Accessories India
System Verilog interview questions part 2
Share This Articale:

System Verilog interview questions part 2 :

Q1. If you have a parent class which have a constructor with argument and a child class which inherts the parent class. If in the child class you dont do the super.new(arg). What will happen ?
Answer : It will give following error : Super class constructor has non-default arguments. Arguments can be specified in the "extends" clause or by calling super.new() explicitly.

You can try the following example with and without commenting the statement :

class parent;
int i;
function new (int i);
i = i;

class child extends parent;
int j, k;
function new (int j, int k);
j = j;
k = k;

program top;

child c1;

c1 = new(2, 3);

Q2. What all the things you will like to add to AVM from RVM

Q3. What is function coverage ? How does it helps. How does you can take feedback from function coverage.

Q4. What is interfaces in SV and wat are advantage of using the interfaces.

Q5. What is virtual interface in system verilog and why do you need it.

Q6. What is the difference between RAND and RANDC.

Q7. What is coverage driven verification.

Q8. What all the components you have in AVM based verification environment.

Q9. What is analysis port in AVM and what port monitor and scoreborad will have

Q10. Can you turn on/off constraints and can u override constraints in system verilog.

Q11. Where you will like to have your assertions and Can you have assertion in your classes.

Q12 : what is automatic keyword in system verilog. Answer :

Q13. What is automatic keyword in system verilog
Q14. what is difference between deep copy and shallow copy

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

Prev << Part 1

Posted By : Ravi - Feb. 27, 2010, 2:57 p.m.

i want to add one point for the code mentioned above. instead of j = j; k = k; it should be this.j = j; this.k = k

Sign In
Login with :-
| | |  
  • Bookmark