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Verilog Interview Questions
How to model Transport and Inertial Delays in Verilog?
Following simple example can illustrate the concept.
module delay(in,transport,inertial);
input in;
output transport;
output inertial;
reg transport;
wire inertial;
// behaviour of delays
always @(in)
begin
transport <= #10 in;
end
assign #10 inertial = in;
endmodule // delay
The timing Diagram for input and outputs
_______ __
in _____| |_____||_______
_______ __
transport _________| |_____||_____
_______
inertial _________| |____________
Non blocking assignment gives you transport delay. Whenever input changes, output is immediately evaluated and kept in a event queue and assigned to output after specified "transport" delay.
In Continuous assign statement the latest event overrides the earlier event in the queue.
I am attaching rudimentary testbench and its output. Hope this helps.
module test;
reg in;
wire transport, inertial;
// instantiate delay module
delay my_delay(in,transport,inertial);
// apply inputs
initial
begin
in = 0;
#20 in = 1;
#20 in = 0;
#30 in = 1;
#5 in = 0;
#30 in = 1;
#30 $finish;
end
// monitor signals
initial
begin
$monitor($time," in = %b transport = %b inertial = %b",
in,transport, inertial);
end
endmodule // test
log file
Compiling source file "delay.v"
Highest level modules:
test
0 in = 0 transport = x inertial = x
10 in = 0 transport = 0 inertial = 0
20 in = 1 transport = 0 inertial = 0
30 in = 1 transport = 1 inertial = 1
40 in = 0 transport = 1 inertial = 1
50 in = 0 transport = 0 inertial = 0
70 in = 1 transport = 0 inertial = 0
75 in = 0 transport = 0 inertial = 0
80 in = 0 transport = 1 inertial = 0
85 in = 0 transport = 0 inertial = 0
105 in = 1 transport = 0 inertial = 0
115 in = 1 transport = 1 inertial = 1
L35 "delay.v": $finish at simulation time 135
81 simulation events
How to display the system date in $display or $write?
(Answers contributed by Swapnajit Mittra and Noman Hassan)
Support of $system() task in Verilog-XL, NC-Verilog and VCS not only allows you to display the system date but also gives you the ability to call any command that you would normally type on the UNIX prompt (C executable, script, standard UNIX command etc.), and would make sense in executing from within Verilog source code.
$system is not an IEEE Standard(1364-1995), but is supported by both XL and VCS.
You could read back in the output of $system, by writing it to another file and reading it back in using $readmemh() as illustrated in following example.
module top;
reg [23:0] today [0:1];
initial
begin
$system("date +%m%d%y > date_file");
// output is 073199 for july 31st 1999
$readmemh("date_file", today);
$display("Today is: %x", today[0]);
end
endmodule
How to display bold characters?
Using following program bold characters can be displayed. Note that this program takes help of UNIX facilities. This may not work on PC based simulators.
module bold;
initial begin
$display ("Normal Text");
$display ("\033[1mBold Text");
$display ("\033[mSwitch back to Normal Text.....");
$display ("\033[7mInverse Text.");
$display ("\033[mSwitch back to Normal Text.....");
$display ("\033[1mBold Text \033[mfollowed by \033[7mInverse text \033[m");
end
endmodule
Sample Verilog Questions asked in Interviews. Please contribute with your questions. If you are looking for answers please refer to website Site FAQ
Differentiate between Inter assignment Delay and Inertial Delay.
What are the different State machine Styles ? Which is better ? Explain disadvantages and advantages.
What is the difference between the following lines of code ?
- reg1<= #10 reg2 ;
- reg3 = # 10 reg4 ;
What is the value of Var1 after the following assignment ?
reg Var1;
initial begin
Var1<= "-"
end
In the below code, Assume that this statement models a flop with async reset. In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or not ?
1 module which_clock (x,y,q,d);
2 input x,y,d;
3 output q;
4 reg q;
5
6 always @ (posedge x or posedge y)
7 if (x)
8 q <= 1'b0;
9 else
10 q <= d;
11
12 endmodule
What is the output of the two codes below ?
1 module quest_for_out();
2
3 integer i;
4 reg clk;
5
6 initial begin
7 clk = 0;
8 #4 $finish;
9 end
10
11 always #1 clk = ! clk;
12
13 always @ (posedge clk)
14 begin : FOR_OUT
15 for (i=0; i < 8; i = i + 1) begin
16 if (i == 5) begin
17 disable FOR_OUT;
18 end
19 $display ("Current i : ‰g",i);
20 end
21 end
22 endmodule
1 module quest_for_in();
2
3 integer i;
4 reg clk;
5
6 initial begin
7 clk = 0;
8 #4 $finish;
9 end
10
11 always #1 clk = ! clk;
12
13 always @ (posedge clk)
14 begin
15 for (i=0; i < 8; i = i + 1) begin : FOR_IN
16 if (i == 5) begin
17 disable FOR_IN;
18 end
19 $display ("Current i : ‰g",i);
20 end
21 end
22 endmodule
Why cannot initial statement be synthesizeable ?
Consider a 2:1 mux; what will the output F be if the Select (sel) is "X" ?
What is the difference between blocking and nonblocking assignments ?
What is the difference between wire and reg data type ?
Write code for async reset D-Flip-Flop.
Write code for 2:1 MUX using different coding methods.
Write code for a parallel encoder and a priority encoder.
What is the difference between === and == ?
What is defparam used for ?
What is the difference between unary and logical operators ?
What is the difference between tasks and functions ?
What is the difference between transport and inertial delays ?
What is the difference between casex and case statements ?
What is the difference between $monitor and $display ?
What is the difference between compiled, interpreted, event based and cycle based simulators ?
What is code coverage and what are the different types of code coverage that one does ?
How do I generate clock in Verilog ?
There are many ways to generate clock in Verilog; you could use one of the following methods:
Method #1
1 initial begin
2 clk = 0;
3 end
4
5 always begin
6 #5 clk = ~clk;
7
8 end
Method #2
1 initial begin
2 clk = 0;
3 forever begin
4 #5 clk = ~clk;
5 end
6 end
Method #3
1 initial begin
2 clk = 0;
3 end
4
5 always begin
6 #5 clk = 0;
7 #5 clk = 1;
8 end
There are many ways to generate clocks: you may introduce jitter, change duty cycle.
How do I test my design xyz ?
To test or verify or validate any design, you need to have a test bench; writing test benches is as difficult as designing itself. Please refer to the Verilog tutorial section in "Art of Writing Test Bench" for more details.
What is the difference between wire and reg ?
Please refer to tidbits section for the difference between wire and reg.
What is the difference between blocking and nonblocking assignment ?
Please refer to tidbits section for difference between blocking and nonblocking statement.
How do I write a state machine in Verilog ?
Please refer to tidbits section for "writing FSM in Verilog".
How do I avoid Latch in Verilog ?
Latches are always bad (I don't like that statement); latches are caused when all the possible cases of assignment to variable are not covered. Well this rule applies to combinational blocks (blocks with edge sensitive lists are sequential blocks); let's look at the following example.
Bad Code
1 always @ (b or c)
2 begin
3 if (b) begin
4 a = c;
5 end
6 end
In the code above, value of a is retained, and it gets changed only when b is set to '1'. This results in a latch. (Need to phrase it right)
Good Code #1
1 always @ (b or c)
2 begin
3 a = 0;
4 if (b) begin
5 a = c;
6 end
7 end
In the code above, no matter what the value of b is, a gets value of '0' first and if b is set to '1' and c is set to '1', only then a gets '1'. This is the best way to avoid latches.
Good Code #2
1 always @ (b or c)
2 begin
3 if (b) begin
4 a = c;
5 end else begin
6 a = 0;
7 end
8 end
In the above code, all the possible cases are covered (i.e. b = 1 and b = 0 case).
How does this xyz code get synthesized ?
Well it is a long story; let me cover that in the synthesis part of Verilog tutorial. You can refer to Actel HDL coding Style. One simple logic is: any code inside always blocks with edge sensitive sensitivity list, results in flip-flops and assign; inside level sensitive always blocks results in combo logic.
How do I implement Memories in Verilog ?
You can implement them by declaring 2-dimension arrays. More details can be found in the Verilog tutorial section "Modeling memories and FSM".
How do I read and write from a file ?
To Read from a file we use $readmemh, where h stands for hex decimal. For writing we use $writememh, $fdisplay, $fmonitor. You could refer to the Verilog tutorial section for more details.
What is this `timescale compiler directive ?
`timescale is used for specifying the reference time unit for the simulator. Syntax of the `timescale is as below:
`timescale /
example : `timescale 10ns/1ns
Timescale directive tends to make more sense at gatelevel simulation than at RTL simulation.
Can we mix blocking and nonblocking in one always block ?
Yes, we can have both blocking and nonblocking code in same always block. Some things that one should know to use this are:
- Blocking assignments are treated as combinational logic.
- One should not assign a variable in the same always block with both blocking and nonblocking assignments.
- Not all synthesis tools support this. (Design compiler supports this).
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