Home System Verilog Interview Questions SV Need of virtual interface
Main Menu
System Verilog
    - Constructs
    - SV Classes
    - Functional Coverage SV
    - Examples
    - Tools
    - Links
    - Books
    - Interview Questions SV
        -- What is callback
        -- What is factory pattern
        -- Logic Reg wire
        -- Need Clocking Block
        -- Ways to avoid race
        -- Coverage Questions
        -- OOP
        -- Need of virtual interface
        -- abstract class
        -- Part 1
        -- Part 2
Open Vera
Digital Concepts
Verification Basics
Interview Questions
Computer Architechture
C and C++
AsicGuru Blog
Tags Cloud
Usefull Sites
Know Your IP/Location
Local Information India
Buy Car/Inverter Batteries
Real Estate India
Sports Accessories India
What is the need of virtual interfaces ?
Share This Articale:

What is the need of virtual interfaces ?

Virtual interfaces provide a mechanism for separating abstract models and test programs from the actual signals that make up the design. A virtual interface allows the same subprogram to operate on different portions of a design and to dynamically control the set of signals associated with the subprogram. Instead of referring to the actual set of signals directly, users are able to manipulate a set of virtual signals. Changes to the underlying design do not require the code using virtual interfaces to be rewritten. By abstracting the connectivity and functionality of a set of blocks, virtual interfaces promote code reuse.

Virtual interfaces can be declared as class properties, which can be initialized procedurally or by an argument to new(). This allows the same virtual interface to be used in different classes. The following example shows how the same transactor class can be used to interact with various different devices:


interface SBus; // A Simple bus interface
logic req, grant;
logic [7:0] addr, data;

class SBusTransctor; // SBus transactor class virtual SBus bus; // virtual interface of type Sbus function new( virtual SBus s ); bus = s; // initialize the virtual interface endfunction
task request(); // request the bus bus.req <= 1'b1; endtask
task wait_for_bus(); // wait for the bus to be granted @(posedge bus.grant); endtask endclass
module devA( Sbus s ) ... endmodule // devices that use SBus module devB( Sbus s ) ... endmodule
module top; SBus s[1:4] (); // instantiate 4 interfaces
devA a1( s[1] ); // instantiate 4 devices devB b1( s[2] ); devA a2( s[3] ); devB b2( s[4] ); initial begin
SbusTransactor t[1:4]; // create 4 bus-transactors and bind t[1] = new( s[1] ); t[2] = new( s[2] ); t[3] = new( s[3] ); t[4] = new( s[4] ); // test t[1:4]
end endmodule


In the preceding example, the transaction class SbusTransctor is a simple reusable component. It is written without any global or hierarchical references and is unaware of the particular device with which it will interact. Nevertheless, the class can interact with any number of devices (four in the example) that adhere to the interface’s protocol.

Keywords : interface   virtual  

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

Prev << OOP

Next >> abstract class

Sign In
Login with :-
| | |  
  • Bookmark