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Covergroup
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System Verilog Covergroup contruct :

Covergroup is like a user defined type that encapsulates and specifies the coverage.  It can be defined in a package, module, program,  interface or class Once defined multiple instances can be created using new Parameters to new() enable customization of different  instances. A covergroup sepcification can include the following components

  1. A clocking event that synchronizes the sampling of coverage points
  2. A set of coverage points
  3. Cross coverage between coverage points
  4. Optional formal arguments
  5. Coverage options


– Ref argument enables different variables to be sampled by different  instances of covergroup

Syntax :

covergroup cg; 
// Covearge points 
endgroup : cg

// create instance 
cg cg_inst = new;

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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