VIA – Protocol signals
•Transfer Pending (TP)
• This signal is driven by the master and is asserted for one clock cycle at the beginning of a transaction. It indicates that a transaction is being initiated on the interconnect.
•Transfer Direction (TD)
• This signal is driven by the master and defines the direction of the transfer and thus the type of the transaction being initiated:
–1 write
–0 read
•Transfer Acknowledge (TA)
–This signal is driven by the slaves and is used to signal the completion of the transaction. A slave not involved in a transaction drives the TA to all logic ’1’ to enable resolution of the acknowledgement signals by an AND network.
–The signal is a bit vector whose value is interpreted as an integer number. Any value between the two extremes is interpreted as a special condition: the transaction is completed but something special occurred during it.

•Transaction attributes (Attr)
• The signals of this class are driven by the master and define the attributes of the transaction. The exact interpretation of the attributes is defined by the application, in a typical arrangement the attributes describe aspects such as the address and the operand size of the transaction.

•Read data (DataR)
–data bus driven by the slave and used in read transactions to transmit the data being read from slave to host.
–A slave not involved in a transaction provides the read data lines with a constant value of all ones to enable the resolution of the read data value using an AND network.
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•Write data (DataW)
–data bus driven by the master and used in write transactions to transmit the data being written from master to slave.
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•Transaction phases
–Each transaction consists of two phases:
•the address phase
•the reply phase.
–The operation of a VIA interconnect is pipelined: the address phase of one transaction can overlap the reply phase of another transaction.

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