AXI protocol – main features
•Properties
–High-bandwidth & low-latency design
–Good performance with long initial latency peripherals
–Flexibility in interconnection architecture
•Features
–Separate address/control and data phases
–Separate read & write channels, request/response channels
–Multiple outstanding addresses
–Out-of-order transaction completion

AXI protocol – the 5 channels

Read and write address channels
Read and write transactions each have their own address channel which carries all of the required address and control information for a transaction.
The following mechanisms are supported:
• variable-length bursts, from 1 to 16 data transfers per burst (AxLEN signal)
• bursts with a transfer size of 8-1024 bits (AxSIZE signal)
• wrapping, incrementing, and non-incrementing bursts (AxBURST signal)
• atomic operations, using exclusive or locked accesses (AxLOCK signal)
• system-level caching and buffering control (AxCACHE signal)
• protection information (AxPROT signal)
• control information on read/write channels are maintained until the corresponding XReady signal is asserted
Read data channel
The read data channel conveys both the read data and read response information
from the slave back to the master. It includes:
• the data bus, which can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide (RDATA)
• a read response indicating the completion status of the read transaction.
• data and response group signals are maintained until the RReady signal is asserted

Write data channel
The write data channel conveys the write data from the master to the slave and includes:
• the data bus, which can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide (WDATA)
• one byte lane strobe for every byte, indicating which bytes of the data bus are valid (WSTRB)
• the last transfer inside a burst must be signalled through the WLAST signal
• data, strobe and wlast information are maintained until the WReady signal is asserted

Write Response channel
The write response channel provides a way for the slave to respond to write transactions.
• All write transactions use completion signaling.
• The completion signal occurs once for each burst, not for each individual data transfer
within the burst.
• Response group signals are maintained until the BReady signal is asserted

AXI Protocol – Transaction Ordering

•Transactions from different masters can complete in any order
•Read and write transactions from the same master can complete in any order
•Done using transaction IDs for each channel
•ARM1176 does not support it yet! ó feature not implemented into RAPU PSS bridges

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