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Control Structures In Open Vera
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Control Structures In Vera :

Following are the control structures supported in Vera. Their behaviour is similar to that of C++ anv Verilog.

1. if-else statement :

In the if - else statement you can execute different block of the code based on the condition. Like

if  ( some_expression ) {

      // if some_expression is true

}

else {

    // if some_expression is false

}

For example :

if ( a > b) {

    printf (" A is greater \n");

}

else {

    printf ("B is greater \n");

}

2. While Loop  :

While loop is used for iterations :

while ( expression ) {

    // body of loop

}

Example:

while ( var != 10 ) {

    var = var + 1; // loop will terminate when the count becomes 10

}

3. For Loop :

For loop is also used for iterations. Syntax : 

for ( initialzation; terminating_expression; loop_variable_increment ) {

    // body of loop

}

Example :

for (var = 0; var <= 10; var++) {

    printf ("var is = %d\n", var);

}

4. Repeat Loop :

Repeat loop executes a loop for the specified number of times. Repeat syntax is

repeat ( expression ) {

    // loop code

}

Example :

integer var;

var = 5;

repeat ( var ) {

    printf ("var is = %d \n", var);

}

6. Case Statement :

Case statement is used in branching when we have lot of options, mainly in the state machines.

case ( case_expression ) {

    < constant_expression_1 > : < statement block >;

    < constant_expression_2 > : < statement block >;

    < default > : < statement block >;

}

Example :

case ( var ) {

    4'b1010 : printf (" var is = %d \n", var);

    4'b1111 : printf (" var is = %d \n", var);

    4'b0000 : printf (" var is = %d \n", var);

    default : printf ("DEFAULT \n");

}

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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