VMM RAL Introduction :

RAL is tool provided by synopsys to implement systemregister and memory space implementation in verification environment.

VMM RAL (Register Abstraction Layer) is a VMM application package used to automate
creating high level, object oriented abstraction model of registers and memory in DUT.
It improves verification productivity by automatically generating verification components for registers – including tests, functional coverage, assertions, backdoor access, and mirroring – from a high-level register specification.

Once you have generated the RAL files they can be compiled with the existing files to verify the connectivity and functinality of the registers.
RAL have a build in functional coverage model. So that you can analyze which registers are accesses in which mode.

Why do we need RAL ?

Normally registers and memories are first to be verified in any verification with reset and readwrite
tests. In present scenario, many times we tend to avoid using abstraction mechanism for
register and memory verification, rather verification engineer may choose to maintain some
register file to keep track of register values on DUT. These models are updated manually every
time new values are written or read from DUT for corresponding register or memory location.
This methodology becomes quite cumbersome when registers count reach in hundreds and that
is common in present day designs. Some verification engineer do use abstraction level of
register and memory verification but still they are not complete solution as they might be missing
broad acceptance and ease of use like VMM RAL.


Also, performing read-back operation on register does not guarantee that design does not have
any interconnect issues. There could still be issue with register addressing, only way to correctly
make sure that no interconnect issue existsis to write to register using physical interface and
then check/verify same value by reading register using hierarchical access to DUT register. The
question then is how frequently do we do it?


Also, think of time it takes to initialize chip level DUT, may be 100 registers to write to start
single test. In reality it takes most of simulation time to initialize DUT and make it ready for data
processing. Now what if we can complete this task of writing to registers in 0 time, yes we can
using BACK DOOR access to register using RAL model. It saves most valuable time in system
level verification by providing 0 time access to read/write Registers.

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start