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Universal Verification Methodology
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Lets start with what and why of UVM :

What is UVM

UVM is standarization in verification methodolgy by accellera. UVM is based on the best features in the existing methodologies OVM/VMM. But it is mostly derived from the OVM methodology and infact its backward compatible with the OVM. It have all the features of the proven OVM methodology and it is based on the System Verilog standard so it will compile on all the simulators which support the system verilog standard.

The main advantages of UVM is :

* Standarized verificication methodogly so no more confusion to choose a methodology to start a project.
* No tool dependency. No more porting issues from one tool to other
* Less confusion for the engineers. Easy to learn and maintain the skill set
* Provides the flexibility and ways to connect the legacy VMM/OVM components
* Backward compatible with OVM and provides the scripts to change OVM environment to UVM.

Why:

Remove the mess of having so many methodologies and provides a standard solution which compiles on all tools.

Index :

        -- Getting Started : Getting started with UVM
        -- Environment Overview : Environment overview
Keywords : Introduction   UVM  

 
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