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Universal verificaton componenent in ovm
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What Is a UVC?

Definition

  • UVC = Universal Verification Component
  • Reusable, pre-verified, configurable, plug-and-play
  • Complete: provides all the logic required for verification

Following the OVM Guidelines

  1. Needs to be re-used and configured as a whole
  2. Architected and packaged in a consistent way

 

Examples

  1. Interface components
  2. Bus-based UVCs (for example, PCI and AHB)
  3. Communication UVCs (for example, Ethernet, MAC, Datalink)
  4. Module-UVCs (for example, UART core, ALU module)

 

Components :

Driver

  • Gets transactions from the sequencer: get_next_item(item)
  • Drives transactions on the DUT interface: send_to_dut(item)
  • Indicates to the sequencer that it is done:  item_done ()  
  • Connects to the DUT via a SystemVerilog virtual interface

 

Monitor

  • Collects information from the DUT
  • Contains events, status, checkers and coverage
  • Monitor is independent of the driver



Sequencer

  • Controls generation of the stimulus
  • Upon request from the driver, generates sequences of transactions

 

Agent

  • Contains instances of the sequencer, driver and monitor
  • Configurable – is_active flag indicates whether the agent is active or passive.
  • is_active == 1 – driver, sequencer and monitor are constructed
  • is_active == 0 – only the monitor is constructed

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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