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ovm sequences
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What is OVM Sequences :

- A sequence is a set of transactions that accomplish a defined complex task for the DUT.

In OVM testcases are typically described at the transaction level which makes them easier to maintain and write for example like we have a packet and instructions etc.

And in many of the scenarios a single transaction can not capture the high level intention of the design so generally a ordered stream of transactions is requried to accompilsh a task.In OVM some sequences are provided as part of a reuseable component.

Sequence Components :

A ovn sequence have three components :

1. Sequences (derived from ovm_sequence)

2. Sequencer (derived from ovm_sequencer)

3. OVM Driver (derived from ovm_driver)

1. Sequences (ovm_sequence) :

  1. It provides a standard test write interface which mean all testcases should be derived from ovm_sequence base class and all follow the same pattern.
  2. Captures intent of the scenario via a set of sequence_items.
  3. It can reuse other predefined scenarios also
  4. It encapsulates timing behaviour etc.

2. OVM Sequencer (ovm_sequencer) :

  1. Controls execution of the stimulus (via sequences )
  2. Provides standard API to connect to a Driver via a consumer interface
  3. Blocking/non-blocking
  4. Provides randomization of sequences and items
  5. Handles parallel sequence execution
  6. Only one transaction can execute on the driver

3. OVM Driver (ovm_driver) :

  1. Also provides a standard API to connect to the sequencer via a producer interface.
  2. Controls when to request the next transaction from sequence driver 
  3. Implements the protocol for driving the transaction on the interface

OVM Sequence Example :

Slide 32
A sequence is a set of transactions that accomplish a defined complex task for the DUT.
class mem_boundry_val_seq extends ovm_sequence #(mem_transfer);

    rand int address;
    rand int data;

    mem_transfer req;
    function new(string name="mem_boundry_val_seq");

    constraint c_addr {
        address < `ADDR_WIDTH'h10;

    `ovm_sequence_utils_begin(mem_boundry_val_seq, mem_master_sequencer)
    `ovm_field_int(address, OVM_ALL_ON)
    `ovm_field_int(data, OVM_ALL_ON)

    virtual task body();
        ovm_report_info(get_type_name(),"STARTING mem_boundry_val_seq ", OVM_LOW);
        while (1) begin
            $display("%0t : mem_boundry_val_seq body() starting...", $time);
            `ovm_do_with(req , { req.addr < `ADDR_WIDTH'h10; req.data == data; } )
            `ovm_do_with(req , { req.addr > 2**`ADDR_WIDTH - 'h10; req.data == data; } )
            $display("%0t : mem_boundry_val_seq item done!", $time);

endclass : mem_boundry_val_seq

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This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start

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