OVM Driver :

Drivers role is to drive the transaction into the dut interface. The driver obtaines the data item from the sequencer for the execation. So all the drivers should be extended from the ovm_driver class either directly or indirectly. The driver have run method which specifies its task and tlm port for communication with the sequencer.

So to create a driver :

1. Derive a driver from the ovm_driver base class
2. If desired, add OVM infrastructure macros for class properties to implement utilities for printing, copying, comparing, and so on.
3. Obtain the next data item from the sequencer and execute.
4. Declare a virtual interface in the driver to connect the driver to the DUT.
5. get_next_item(req) to get next item
6. item_done() to indicate we are done with data item

OVM Driver example :

class mem_master_driver extends ovm_driver #(mem_transfer);

    protected virtual mem_if m_if;

    protected int master_id;

    `ovm_object_utils_begin (mem_master_driver)
        `ovm_field_int (master_id, OVM_ALL_ON)
    `ovm_object_utils_end

    function new  (string name = "mem_master_driver", ovm_component parent=null);
        super.new (name, parent);
    endfunction : new

    function void assign_vi (virtual interface mem_if if_in);
        this.m_if = if_in;
    endfunction : assign_vi
virtual task run () ;
        $display("INSIDE RUN : DRIVER CLK = %x\n", m_if.CLK);
        fork
            drive_signals();
        join
    endtask : run

    task drive_signals ();
        forever begin
            @(posedge m_if.CLK);
            seq_item_port.get_next_item(req);
            drive_transfer (req);
            seq_item_port.item_done();
        end
    endtask : drive_signals

    task drive_transfer (mem_transfer req);
        m_if.A = req.addr;
        m_if.D = req.data;
        case (req.read_write)
            READ : m_if.WX = 1'b1;
            WRITE : m_if.WX = 1'b0;
        endcase
        m_if.WRENX = req.write_enable;
        m_if.EX = req.chip_enable;
        // Disable the chip enable in next clock cycle
        repeat (2) @ (posedge m_if.CLK);
        m_if.EX = 1'b1;
    endtask : drive_transfer

endclass : mem_master_driver

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