Home Methodologies OVM Example
Main Menu
Home
System Verilog
Verilog
Methodologies
    - OVM Tutorial
    - OVM Example
        -- Sample DUT
        -- Sequence Item
        -- OVM Driver
        -- OVM Monitor
        -- OVM Sequencer
        -- OVM Scoreboard
        -- OVM Env
        -- OVM Env
        -- Dut Interface
        -- Top Level
        -- OVM Test
        -- OVM Sequence
    - UVM
    - VMM
    - VMM RAL
    - VMM Example
    - AVM Tutorial
Open Vera
Digital Concepts
Verification Basics
Protocols
Scripting
Articles
Videos
Interview Questions
Computer Architechture
C and C++
Blog/Article
AsicGuru Blog
Tags Cloud
Ads
Usefull Sites
Know Your IP/Location
Local Information India
Free Classified India
Real Estate India
OVM Example
Share This Articale:

OVM Example -

A very simple memory example which explains the basic ovm concepts with a very simple memory dut. The example is compiled and simlulated with Modelsim/Questasim 6.4. It should run with VCS and NC as well.

To run the example you need to make few changes like

  1. Changing the OVM Path in the mem_comp.f file
  2. Setting up modelsim environement and changing the modelsim command etc.

You can download the full example by clicking here :

OVM Example Memory TB(ovm_example_memtb.tar.gz)

 

 

Index :

        -- Sample DUT :
        -- Sequence Item :
        -- OVM Driver :
        -- OVM Monitor :
        -- OVM Sequencer :
        -- OVM Scoreboard :
        -- OVM Env :
        -- OVM Env :
        -- Dut Interface :
        -- Top Level :
        -- OVM Test :
        -- OVM Sequence :
Keywords : ovm example   writting testbench with ovm  

Because of huge spamming only registered users are allowed to comment. Please Login or Register

 
Login/Register
Register
Sign In
Bookmark
ADS