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What is AVM
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Introduction to AVM :

  1. Library of modular, reusable verification components
    1. Implemented in both System Verilog and SystemC
    2. Consistent Transaction-Level interfaces with common semantics
  2. Infrastructure details built in so you don’t have to worry about them.
    1. Simple connections between components
    2. Controllable, customizable error/message reporting
  3. Open-Source means we are free to use them, with full access to all the source code

Why Do we need a verification methodology :

  1. Reusability
  2. Observability
  3. Controllability
  4. Measurability
  5. Automation

 

AVM Layering :

 

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


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