Home Methodologies AVM Tutorial AVM Components
Main Menu
Home
System Verilog
Verilog
Methodologies
    - OVM Tutorial
    - OVM Example
    - UVM
    - VMM
    - VMM RAL
    - VMM Example
    - AVM Tutorial
        -- Introduction
        -- AVM Components
        -- Analysis Port export
        -- TLM In AVM
        -- Analysis Port
        -- TLM Channels
        -- Components
        -- Transaction
        -- Transactor
        -- Environment
        -- Messaging
Open Vera
Digital Concepts
Verification Basics
Protocols
Scripting
Articles
Videos
Interview Questions
Computer Architechture
C and C++
Blog/Article
AsicGuru Blog
Tags Cloud
Ads
Usefull Sites
Know Your IP/Location
Local Information India
Buy Car/Inverter Batteries
Real Estate India
Sports Accessories India
Components in AVM Based testbench
Share This Articale:

AVM Compoments :

1. Transactor :

Converts traffic between signal and transaction domains

 

2. Monitor

Converts signal level traffic to a stream of transactions Checks for protocol violations Moves traffic from the design to analysis portion of the TB

 

3. Driver

Is a Transactor that takes an active part in the protocol Interprets transactions and drives signal level bus May be bi-directional

 

4. Responder

Is the mirror image of a Driver. It plays an active part in the protocol. It identifies a response and forwards it to the slave It takes the response from the slave and applies it to the bus

 

5. Stimulus Generator

Generates sequences of transactions that are sent into the test bench Generate constrained random stimulus; or Generate directed stimulus

6. Master

  1. Bi-directional component
  2. Initiates activity

7. Slave

  1. Bi-directional component
  2. Response to activity

This Articles is written/submitted by puneet (Puneet Aggarwal). You can also contribute to Asicguru.com. Click here to start


Prev << Introduction

Next >> Analysis Port export

 
Login/Register
Register
Sign In
Login with :-
gmail-yahoo-twitter-facebook
| | |  
  •  
  • Bookmark
    ADS