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Analysis Port in System Verilog
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Analysis Port in OVM :

Simple Fifo Example :
// Produce Class
class producer extends verif_component;
tlm_put_if #( int ) put_port;
task run();
for( int i = 0; i < 10; i++ )
begin
$display("about to put %d",i);
put_port.put( i );
end
endtask;
endclass
// Consumer Class
class consumer extends verif_component;
tlm_get_if #( int ) get_port;
task run();
int i;
forever
begin
get_port.get( i );
$display( "Just got %d" , i );
end
endtask
endclass
class producer extends verif_component;
tlm_put_if #( int ) put_port;
task run();
for( int i = 0; i < 10; i++ )
begin
$display("about to put %d",i);
put_port.put( i );
end
endtask;
endclass
class consumer extends verif_component;
tlm_get_if #( int ) get_port;
task run();
int i;
forever begin
get_port.get( i );
$display( "Just got %d" , i );
end
endtask
endclass
// Environement Class
class env;
producer p = new;
consumer c = new;
tlm_fifo #( int ) f = new;
function void connect;
// Connect Port and Export
p.put_port = f.blocking_put_export;
c.get_port = f.blocking_get_export;
endfunction
endclass
// Top Level Program
program top;
env = new();
initial begin
env.connect();
verif_component::run_all_threads();
end
endprogram
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