How many among you know that you can actually display color messages using Verilog and SystemVerilog?

You can implement a logic in your testbench to have nicely colored display messages at the end of your simulation which will give you a PASS/FAIL messages. I have written a piece of code given below and you can refer the same. I have captured a snapshot of output which you can see below.

program clr_display();
  class color ;
    task display ();
      $display("%c[1;34m",27);
      $display("***************************************");
      $display("*********** TEST CASE PASS ************");
      $display("***************************************");
      $write("%c[0m",27);
      
      $display("%c[1;31m",27);
      $display("***************************************");
      $display("*********** TEST CASE FAIL ************");
      $display("***************************************");
      $display("%c[0m",27);
    endtask
  endclass

  initial 
    begin
      color clr;
      clr = new ();
      clr.display ();
  end
endprogram


OUTPUT:




The message to be printed is ("%c[TYPE;COLOURm",27);.

TYPE specifies how the message should be?

1 set bold
2 set half-bright (simulated with color on a color display)
4 set underscore (simulated with color on a color display)
5 set blink
7 set reverse video

COLOR specifies the message color.

30 set black foreground
31 set red foreground
32 set green foreground
33 set brown foreground
34 set blue foreground
35 set magenta foreground
36 set cyan foreground
37 set white foreground


With an above example you can have a display messages with colors. So this way you can have nicely and colored messages on your terminal.

Enjoy...!

-ASIC With Ankit (www.asicwithankit.blogspot.com)

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