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Tutorials on System verilog, Verilog, Open Vera, Verification, OVM, VMM, AXI, OCP
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Welcome to AsicGuru.com
On Asicguru.com You will find some good material related to Asic Design and Verification. Here you will some good tutorials, examples on
- System Verilog Tutorial - In System Verilog Section you will find tutorials on Sytem verilog constructs, Classes, OOPS, Functional Coverage, Interface, examples etc
- Open Vera - In Open Vera Secion you will find tutorial on open vera language, contstructs, arrays, classes, interfaces etc
- Verification Methodologies
- OVM Tutorial (Open Vera Methodologie)
- VMM Tutorial (Verification manual methodologie)
- Verilog
- Verification Basics
- Scripting Tutorial - Perl, Python
- Perl
- Makefile
- Bash
- Python
This site is maintained by Puneet Aggarwal from Bangalore, India. I am working as Senior Design Engineer with AMD. I have done BTech in computer engg. from Kurukshetra University. Any comments or feeback please write to me at er.punit at gmail.com. Click here to view my linked in profile : http://in.linkedin.com/in/puneetworld
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Posted By : LnddMiles - 2009-07-27 06:29:48
Pretty cool post. I just stumbled upon your blog and wanted to say that I have really liked reading your blog posts. Anyway I’ll be subscribing to your blog and I hope you post again soon!